Skip to main menu
Scroll to content
PL
|
EN
Full-text resources of PSJD and other databases are now available in the new Library of Science.
Visit
https://bibliotekanauki.pl
Search
Browse
About
test
PL
EN
BibTeX
PN-ISO 690:2012
Chicago
Chicago (Author-Date)
Harvard
ACS
ACS (no art. title)
IEEE
Preferences
Polski
English
Language
enabled
[disable]
Abstract
10
20
50
100
Number of results
Tools
PL
EN
BibTeX
PN-ISO 690:2012
Chicago
Chicago (Author-Date)
Harvard
ACS
ACS (no art. title)
IEEE
Link to site
Copy
Journal
International Journal of Electronics and Telecommunications
2019
|
65
|
3
|
Article title
Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks
Authors
P. Velrajkumar
,
C. Senthilpari
,
J. Sheela Francisca
,
T. Nirmal Raj
Content
Full texts:
Download
Title variants
Languages of publication
PL
Abstracts
Keywords
PL
FPGA
Model Sim
Power dissipation
speed
Universal Logic
Nauki Techniczne
Publisher
Polska Akademia Nauk
Journal
International Journal of Electronics and Telecommunications
Year
2019
Volume
65
Issue
3
Physical description
Contributors
author
P. Velrajkumar
author
C. Senthilpari
author
J. Sheela Francisca
author
T. Nirmal Raj
References
Document Type
Publication order reference
Identifiers
YADDA identifier
bwmeta1.element.oai-journals-pan-pl-113306
JavaScript is turned off in your web browser. Turn it on to take full advantage of this site, then refresh the page.