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Reducing Leakage Power for SRAM Design Using Sleep Transistor

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Khandelwal S., Akashe S., Sharma S.

Acta Physica Polonica A

2013

vol. 123

issue 2

185-187

Low power design is the industry buzzword these days in present chip design technologies. Caches occupy around 50% of the total chip area and consume considerable amount of power. This project's focus is to reduce leakage power consumption of an 8 kbit SRAM by employing techniques like power gating. The main technique used in power gating is the use of sleep transistor. In our design we have chosen a stack-based implementation.

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1 Acta Physica Polonica A

1 2013

1 Akashe S.

1 Khandelwal S.

1 Sharma S.

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Reducing Leakage Power for SRAM Design Using Sleep Transistor