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2016 | 53 | 3 | 404-416
Article title

Comparative study on transistor based full adder designs

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EN
Abstracts
EN
Recently in the generic systems the load on the processor is much heavy. The ability and the challenging process have ended with larger core operations are in the core processor. This paper is basically given special importance on different methodologies having been proposed for Adder, which is the basic operation of the Arithmetic unit. The wide research on the digital adders has been covered so many applications like designs of ALU, RISC, CISC processors, DSP used for data path arithmetic, low power CMOS, optical computing, Nanotechnology and so on. This paper gives greater knowledge and understanding about the various techniques that have amply used of Adder from the earlier years. In this paper we analyzed the implementation of different types of full Adders implemented using CMOS logic (Static CMOS and Dynamic CMOS), CMOS Transmission Gates, Pass Transistor Gates (CPL and DPL).
Publisher

Year
Volume
53
Issue
3
Pages
404-416
Physical description
Contributors
author
  • School of Electronics Engineering, VIT University, Vellore, Tamil Nadu, India, ranitha@vit.ac.in
References
  • [1] Karthik Reddy G., ”Low Power-Area Designs Of 1bit Full Adder In Cadence Virtuoso Platform”. International Journal of VLSI design & Communication Systems (VLSICS) Vol. 4, No. 4, August 2013.
  • [2] N. Zhuang and H. Wu, “A New Design of the CMOS Full Adder”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 5, May 1992.
  • [3] R. Zimmermann and W. Fichtner. “Low-Power Logic Styles: CMOS Versus Pass - Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1079-1090, July 1997.
  • [4] R. Shalem, E. John, and L. K. John, “A Novel Low-power Energy Recovery Full Adder Cell”, Proceedings of Great Lakes Symp. VLSI, pp. 380-383, Feb. 1999.
  • [5] M. Vesterbacka, “Signal Processing Systems”, IEEE Conference Publications, pp. 751- 753, Oct. 1999.
  • [6] D. Radhakrishnan, “Low-Voltage Low-Power CMOS Full Adder”, IEE Proc. -Circuits Devices Systems, Vol. 148, No. I, February 2001.
  • [7] H.T. Bui, Y. Wang, and Y. Jiang. “Design and Analysis of Low-Power 10-transistor Full Adders using XOR-XNOR gates”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, Vol. 49, no. 1, pp. 25-30, Jan. 2002.
  • [8] Y. Jiang, A. A. Sheraidah, Y. Wang, E. Sha, and J. G. Chung. “A Novel Multiplexerbased Low-Power Full Adder”, IEEE Trans. Circuits Syst. II. Vol. 51, pp. 345-348, Jul. 2004.
  • [9] F. Vasefi and Z. Abid. “Low Power N-bit Adders and Multiplier Using Lowest Number of Transistors 1-bit Adders”, IEEE Conference Proceeding of CCECE/CCGEI, Saskatoon, pp. 1731-1734, May 2005.
  • [10] K. Navi and O. Kavehei, “Low-Power and High-Performance 1-Bit CMOS Full- Adder Cell”, Journal of Computers, Vol. 3, No. 2, pp. 48-54, February 2008.
  • [11] M. Hosseinghadiry, H. Mohammadi and M. Nadisenejani. “Two New Low-Power High-Performance Full Adders with Minimum Gates”, Journal of Computers, Vol. 4, No. 2, pp. 119-126, Feb. 2009.
  • [12] Tripti Sharma, K.G. Sharma, Prof. B.P. Singh and Neha Arora. “A Novel CMOS 1-bit 8T Full Adder Cell”, World Scientific and Engineering Academy and Society (WSEAS) Transactions on Systems, Vol. 9, No.3, pp. 317-326, March 2010. H Index: 9.
  • [13] Shivshankar Mishra, V. Narendar and Dr. R. A. Mishra. “On the Design of High- Performance CMOS 1-Bit Full Adder Circuits”, Proceedings published by International Journal of Computer Applications, pp. 1-4, 2011.
  • [14] Deepa Sinha, Tripti Sharma, K. G. Sharma and Prof. B. P. Singh. “ Ultra Low Power 1-Bit Full Adder”, International Symposium on Devices MEMS, Intelligent Systems & Communication (ISDMISC), Proceedings published by International Journal of Computer Applications (IJCA), pp. 09-11, 2011. Impact factor: 0.814.
  • [15] M. Kumar, S. K. Arya and S. Pandey. “Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate”, International Journal of VLSI design & communication Systems (VLSICS), Vol. 2, No. 4, pp. 47-59, December 2011.
  • [16] Bazzazi, A. Mahini and J. Jelini. “Low Power Full Adder Using 8T Structure”, Proceedings of the IMECS 2012 Vol. II, Hong Kong, 14-16 March 2012.
  • [17] M. Geetha Priya, K. Baskaran.” Low Power Full Adder With Reduced Transistor Count” International Journal of Engineering Trends and Technology (IJETT) – Volume 4, Issue 5 May, 2013.
  • [18] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison- Wesley, 4th Ed.
  • [19] S. Kang and Y. Leblebici, “CMOS Digital Integrated Circuits, Analysis and Design”, Tata McGraw-Hill, 3rd Ed.
  • [20] J.P. Uyemura. “Introduction to VLSI Circuits and Systems”, John Wiley and Sons, 2002.
  • [21] K. Bernstein, K. M. Carrig, C. M. Durham, P. R. Hansen, D. Hogenmiller, E. J. Nowak, and N. J. Rohrer, “High-Speed CMOS Design Styles”, Kluwer Academic Publishers, 1st Ed., 1999.
  • [22] Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolić, Digital Integrated Circuits: A Design Perspective, Pearson Education.
Document Type
article
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YADDA identifier
bwmeta1.element.psjd-679db92d-b6f3-4e84-b2d5-4de9fbe734dc
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