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2019 | 121 | 26-34
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Low Power PLL for Communication System

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This paper presents the design aspects of low power digital PLL. The performance determining parameters of a digital PLL are lock range, capture range, jitter in generated output signal and power consumption. Its performance is mainly governed by two building blocks namely the voltage controlled oscillator (VCO) and phase detector. We have performed the complete analysis of phase noise and power consumption of current starved VCO, a novel D flip-flop based phase detector and transmission gate based charge pump. We have introduced a charge pump which is giving a remarkable reduction in reference spur. As PLL is used for many applications like as a frequency synthesizer, for clock deskewing, for jitter reduction, in FM radios so everyone demands a low cost low power highly integrated PLL design. Best efforts have been made to design a MOSFET based low power, low cost GHz range digital PLL. The main objective of this paper is to design a low power digital PLL which produces a very stable clock signal having jitter less than 1ps, power consumption less than 805uw ,output frequency ranged from 0 to380MHz at a supply voltage of 1.8V.
Physical description
  • Department of Electronics & Communication Engineering, KIET Group of Institutions, Ghaziabad, India
  • [1] Won - Hyo Lee, Jun - Dong Cho, Sung - Dae Lee, A High Speed and Low Power Phase-Frequency Detector and Charge – pump. Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific. DOI: 10.1109/ASPDAC.1999.760011
  • [2] Hua, Di, Xiaoping Liao and Yongchang Jiao. A MEMS phase detector at X-band based on MMIC technology. 2009 IEEE Sensors (2009): 506-508. DOI: 10.1109/ICSENS.2009.5398287
  • [3] Muhammad Adeel Ansari, Waqar Ahmad, Qiang Chen, Li-Rong Zheng, Diode Based Charge Pump Design using 0.35 μm Technology. NORCHIP 2010. DOI: 10.1109/NORCHIP.2010.5669437
  • [4] M. Young, The Technical Writer's Handbook. MillValley, CA: University Science, 1989.
  • [5] Calogero Marco Ippolito ; Alessandro Italia ; Giuseppe Palmisano . An ultra low-power CMOS frequency synthesizer for low data-rate sub-GHz applications. 2010 Proceedings of ESSCIRC. DOI: 10.1109/ESSCIRC.2010.5619831
  • [6] D. Duarte ; S. Hsu ; K. Wong ; M. Huang ; G. Taylor . Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. IEEE Custom Integrated Circuits Conference 2010. DOI: 10.1109/CICC.2010.5617473
  • [7] Maneatis, J. G. Low-jitter and process independent DLL and PLL based on self biased techniques. IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC (1996): 130-131. DOI:10.1109/JSSC.1996.542317
  • [8] D. Birru, A novel delay-locked loop based CMOS clock multiplier. IEEE Trans. Consumer Electron, vol. 44, no. 4, pp. 1319-1322, Nov. 1998.
  • [9] D. Birru. A novel delay-locked loop based CMOS clock multiplier. IEEE Transactions on Consumer Electronics Volume 44 Issue 4, Nov. 1998, 1319-1322. DOI: 10.1109/30.735832
  • [10] Roland E. Best. Phase-Locked Loops: Theory, Design, and Applications. 2 nd Ed. New York, NY: McGraw - Hill, 1993. ISBN-13: 978-0079113863
  • [11] Vaclav Valenta, Martine Villegas, Genevieve Baudoin. Analysis of a PLL Based Frequency Synthesizer using Switched Loop Bandwidth for Mobile WiMAX. 18th International Conference Radioelektronika, Radioelektronika 2008, Apr 2008, Prague, Czech Republic. ISBN: 978-1-4244-2087-2, 2008
  • [12] Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery circuits: Tbeory and Design. 508 pages, April 1996, Wiley-IEEE Press, ISBN: 978-0-7803-1149-7
  • [13] Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1993.
  • [14] G.R. Aiello, G.D. Rogerson. Ultra-wideband wireless systems. IEEE Microwave Magazine Volume: 4, Issue: 2 , June 2003, Page(s): 36 – 47. DOI: 10.1109/MMW.2003.1201597
  • [15] M.M. Reja, Z. Hameed, K. Moez, S. Shamsadini, Compact CMOS IR-UWB transmitter using variable-order Gaussian pulse generator. Electronics Letters, vol. 49, no. 16, pp. 1038-1040, 2013.
  • [16] Bonghyuk Park, Kwangchun Lee, Sangsung Choi, Songcheol Hong, "The design of integrated 0.13-μm CMOS receiver for ultra-wideband systems", Microwave and Optical Technology Letters, vol. 52, pp. 841, 2010.
  • [17] Hu Yonghong, Shielding box antenna for application in WUSB flash disk. Microwave and Optical Technology Letters, vol. 52, pp. 1633, 2010.
  • [18] Raj Kumar, K. K. Sawant, Design of CPW-FEED inscribed square circular fractal antenna for UWB applications. Microwave and Optical Technology Letters, vol. 53, pp. 1079, 2011
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