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2018 | 113 | 194-209
Article title

Capacitance/Resistance Modeling and Analog Performance Evaluation of 3-D SOI FinFET Structure for Circuit Perspective Applications

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EN
Abstracts
EN
This paper explores the capacitance and resistance modeling of 3-D (dimensional) SOI FinFET structure and circuit implementation approach is done for the utility of SOI FinFET structure. The scaling of the FinFET structure is continuously ongoing and increased parasitic and resistance affects the circuit level performance of SOI FinFET in ICs (Integrated Circuits) below 20 nm technology node. A geometrical-based analysis is done to get the optimized parasitic capacitance and resistance model and validity of the model is verified by three-dimensional (3-D) field solver Synopsys Raphael software. For utility of the developed model, some circuit implementation is done in h-spice simulation environment.
Discipline
Year
Volume
113
Pages
194-209
Physical description
Contributors
author
  • Department of Electronics and Communication Engineering, D. B. R. Ambedkar National Institute of Technology (NIT), Jalandhar (Punjab), 144011, India
author
  • Department of Electronics and Communication Engineering, Dr. B. R. Ambedkar National Institute of Technology (NIT), Jalandhar (Punjab), 144011, India
References
  • [1] J. P. Colinge, Multiple-gate SOI MOSFETs. Solid State Electron. vol. 48(6) (2004) 897–905.
  • [2] J. P. Colinge, A. Chandrakasan, FinFETs and other multi-gate transistors. Springer, 2008.
  • [3] D. Bhattacharya, N. K. Jha, FinFETs: From Devices to Architectures. Adv. Electron. Volume 2014, Article ID 365689, 21 pages. http://dx.doi.org/10.1155/2014/365689
  • [4] ITRS, International technology roadmap for semiconductors 2013; Executive Summary.(2013) 80.
  • [5] H. M. Fahad, C. Hu, M. M. Hussain, Simulation study of a 3-D device integrating FinFET and UTBFET. IEEE Transaction Electron Devices. 62( 1) (2015) 83–87.
  • [6] D. Hisamoto et al., FinFET-A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transaction. Electron Devices. 47(2) (2000) 2320–2325.
  • [7] E. J. Nowak et al., Turning silicon on its edge [double gate CMOS/FinFET technology]. Circuits Devices Magzine IEEE. 20(1) (2004) 20–31.
  • [8] P. Magnone et al., Matching performance of FinFET devices with fin widths down to 10 nm. IEEE Electron Device Letter 30(12) (2009) 1374.
  • [9] N. Jain, B. Raj, Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications. Journal of Nanoelectronics Optoelectronics 13(4) (2018) 531–539
Document Type
article
Publication order reference
Identifiers
YADDA identifier
bwmeta1.element.psjd-15f715b6-47ab-445e-9eb6-e059cf510f09
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