PL EN


Preferences help
enabled [disable] Abstract
Number of results
- |
Article title

Synthesis of 2-level combinatorial circuits with PKmin

Content
Title variants
Languages of publication
PL
Abstracts
PL
In this paper a new design tool is presented that is useful in automated synthesis of combinatorial logic. PKmin program is devoted for synthesis of 2-level circuits composed of gates and PLAs, multi-level circuits and a functional decomposition of logical functions for LUT-based logic implementations in FPGA. It has been built on the basis of the research conducted at Cracow University of Technology. In the paper design algorithms implemented in PKmin are mutually compared. Then, an experimental efficiency comparison of gate and PLA-based 2-level synthesis with PKmin and Espresso design tools is reported.
Publisher
Year
-
Physical description
Dates
online
2015-04-29
Contributors
References
Document Type
Publication order reference
Identifiers
YADDA identifier
bwmeta1.element.ojs-nameId-6e3e8ea9-5a94-37a7-828b-e6cd5da23db6-year-2015-article-2024
JavaScript is turned off in your web browser. Turn it on to take full advantage of this site, then refresh the page.