Java Based Transistor Level CPU Simulation Speedup Techniques

• Authors: Tomasz Wojtowicz
• Languages of publication: PL

Abstracts

PL

Transistor level simulation of the CPU, while very accurate, brings also the performance challenge. MOS6502 CPU simulation algorithm is analysed with several optimisation techniques proposed. Application of these techniques improved the transistor level simulation speed by a factor of 3–4, bringing it to the levels on par with fastest RTL-level simulations so far.

Keywords

PL

CPU, microarchitecture, simulation, registers, pipeline, activity, 6502

• Publisher: [unknown2]
• Journal: Schedae Informaticae
• Year: 2015
• Volume: 24

Dates

published

2015

online

06 - 07 - 2016

Contributors

author

Tomasz Wojtowicz