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2016 | 130 | 1 | 223-225
Article title

Ultra-Low Voltage VDCC Design by Using DTMOS

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Languages of publication
EN
Abstracts
EN
In this paper, a new ultralow voltage and ultralow power voltage differencing current conveyor based on dynamic threshold voltage MOS transistors was proposed. The simulations were performed by using LTSpice Program with TSMC CMOS 0.18 μ m process parameters. A new notch filter configuration was also presented as an application for the proposed voltage differencing current conveyor. The power consumption of proposed voltage differencing current conveyor was simply 12.42 nW at symmetric ± 0.2 V supply voltage. The simulation results were found in close agreement with the theoretical results.
Keywords
EN
Publisher

Year
Volume
130
Issue
1
Pages
223-225
Physical description
Dates
published
2016-07
Contributors
author
  • Yildiz Technical University, Faculty of Naval Architecture and Maritime, Istanbul 34349, Turkey
author
  • Istanbul University, Department of Electrical and Electronics Engineering, Istanbul, 34850, Turkey
References
  • [1] L. Benini, G. De Micheli, E. Macii, IEEE Circuits Syst. Mag. 1, 6 (2001), doi: 10.1109/7384.928306
  • [2] A.J. Annema, B. Nauta, R. Van Langevelde, H. Tuinhout, IEEE J. Solid-State Circuits 40, 132 (2005), doi: 10.1109/JSSC.2004.837247
  • [3] K. Nagaraj, IEEE Trans. Circuits Syst. 36, 1210 (1989), doi: 10.1109/31.34666
  • [4] Xinbo Qiao, Yong Ping Xu, Xiaoping Li, Analog Integrat. Circuits Sign. Process. 44, 201 (2005), doi: 10.1007/s10470-005-3007-x
  • [5] A. Uygur, H. Kuntman, Radioengineering 22, 458 (2013)
Document Type
Publication order reference
Identifiers
YADDA identifier
bwmeta1.element.bwnjournal-article-appv130n1057kz
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