PL EN


Preferences help
enabled [disable] Abstract
Number of results
2015 | 128 | 2B | B-78-B-81
Article title

The Modeling and Hardware Implementation of Semiconductor Circuit Elements by Using ANN and FPGA

Authors
Content
Title variants
Languages of publication
EN
Abstracts
EN
This study, the modeling and hardware implementation of semiconductor circuit elements very frequently used in electronic circuits are carried out by using artificial neural networks and field programmable gate array chip. Initially the artificial neural network models obtained has been written in very high speed integrated circuit hardware description language (VHDL). Then, these configurations have been simulated and tested under ModelSim Xilinx software. Finally, the best configuration has been implemented under the Xilinx Spartan-3E FPGA (XC3S500E) chip of Xilinx. The modeling of electronic circuit elements is very important both in respect of engineering, and in respect of practical mathematics. The main aim is to shorten the simulation time and to examine the real physical system applications easily by using the model elements instead of using the ones used in real applications. The effectiveness of the implemented artificial neural network models on field programmable gate array was found successful.
Keywords
EN
Contributors
author
  • Yuzuncu Yil University, Ercis Technical Vocational School of Higher Education, Electronic and Communication Technologies, Van, Turkey
References
  • [1] T.A. York, Microproc. Microsyst. 17, 371 (1993), doi: 10.1016/0141-9331(93)90059-G
  • [2] D.K. Iakovidis, D.E. Maroulis, D.G. Bariamis, Microproc. Microsyst. 31, 160 (2007), doi: 10.1016/j.micpro.2006.02.013
  • [3] J. Li, D. An, L. Lang, D. Yang, Proc. Eng. 29, 2633 (2012), doi: 10.1016/j.proeng.2012.01.363
  • [4] K. Kompton, S. Hauck, ACM Comput. Surv. 34, 171 (2002), doi: 10.1145/508352.508353
  • [5] J. Lu, L. Jing, Proc. Eng. 16, 858 (2011), doi: 10.1016/j.proeng.2011.08.1166
  • [6] G. Krampl, M. Rona, Microelectron. J. 33, 855 (2002), doi: 10.1016/S0026-2692(02)00092-7
  • [7] P. Ferreira, P. Ribeiro, A. Antunes, F.M. Dias, Neurocomputing 71, 71 (2006), doi: 10.1016/j.neucom.2006.11.028
  • [8] S.K. Mandal, S. Sural, A. Patra, IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 27, 188 (2008), doi: 10.1109/TCAD.2007.907284
  • [9] D. Shen, L. Jin, X. Ma, Lect. Notes Comput. Sci. 3173, 988 (2004), doi: 10.1007/978-3-540-28647-9_163
  • [10] O. Polat, T. Yıldırım, Digit. Sign. Proc. 20, 881 (2010), doi: 10.1016/j.dsp.2009.10.013
  • [11] H. Mekki, A. Mellit, H. Salhi, B. Khaled, AIP Conf. Proc. 1019, 211 (2008), doi: 10.1063/1.2952981
  • [12] S. Saadi, A. Guessoum, M. Bettayeb, Microproc. Microsyst. 37, 52 (2013), doi: 10.1016/j.micpro.2012.09.013
  • [13] S. Li, M. Moussa, S. Areibi, Canad. J. Electric. Comput. Eng. 31, 31 (2006), doi: 10.1109/CJECE.2006.259201
  • [14] H. Mekki, A. Mellit, S.A. Kalogirou, A. Messai, G. Furlan, Prog. Photovolt. Res. Appl. 18, 115 (2010), doi: 10.1002/pip.950
Document Type
Publication order reference
Identifiers
YADDA identifier
bwmeta1.element.bwnjournal-article-appv128n2b021kz
JavaScript is turned off in your web browser. Turn it on to take full advantage of this site, then refresh the page.