Reducing Leakage Power for SRAM Design Using Sleep Transistor

• Authors: S. Khandelwal , S. Akashe , S. Sharma
• Languages of publication: EN

Abstracts

EN

Low power design is the industry buzzword these days in present chip design technologies. Caches occupy around 50% of the total chip area and consume considerable amount of power. This project's focus is to reduce leakage power consumption of an 8 kbit SRAM by employing techniques like power gating. The main technique used in power gating is the use of sleep transistor. In our design we have chosen a stack-based implementation.

Keywords

EN

85.40.-e

Discipline

• 85.40.-e: Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology(see also 85.45.-w Vacuum microelectronics; 84.40.Lj Microwave integrated electronics; 42.82.-m Integrated optics; 85.25.Hv Superconducting logic elements and memory devices; microelectronic circuits)

• Publisher: Institute of Physics, Polish Academy of Sciences
• Journal: Acta Physica Polonica A
• Year: 2013
• Volume: 123
• Issue: 2
• Pages: 185-187

Dates

published

2013-02

Contributors

author

S. Khandelwal

• Research Scholar, Department of Electronics & Communication Engineering, RGPV University, Bhopal, M.P, India

author

S. Akashe

• Research Scholar, Department of Electronics & Communication Engineering, Thapar University, Patiala, Punjab, India

author

S. Sharma

• Department of Electronics & Communication Engineering, Thapar University, Patiala, Punjab, India

References

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Identifiers

DOI

10.12693/APhysPolA.123.185