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2013 | 123 | 2 | 185-187
Article title

Reducing Leakage Power for SRAM Design Using Sleep Transistor

Content
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Languages of publication
EN
Abstracts
EN
Low power design is the industry buzzword these days in present chip design technologies. Caches occupy around 50% of the total chip area and consume considerable amount of power. This project's focus is to reduce leakage power consumption of an 8 kbit SRAM by employing techniques like power gating. The main technique used in power gating is the use of sleep transistor. In our design we have chosen a stack-based implementation.
Keywords
EN
Year
Volume
123
Issue
2
Pages
185-187
Physical description
Dates
published
2013-02
References
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  • [5] M. Anis, M. Elmasry, Multi-threshold CMOS Digital Circuits-Managing Leakage Power, 1 Ed., Springer, 2003
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  • [7] S. Tyagi, M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, W. Chen, B. Crew, M. Hussein, P. Jacob, C. Kenyon, C. Lo, B. McIntyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, TS. hompson, B. Tufts, J. Xu, S. Yang, M. Bohr, in: Int. Electron Devices Meeting, 2000, Technical Digest. 2000, p. 567
  • [8] A. Ramalingam, B. Zhang, A. Devgan, D.Z. Pan, in: Asia and South Pacific Design Automation Conference - ASP-DAC, ACM, New York 2005, p. 1094
  • [9] Z. Zhang, Z. Guo, Active Leakage Control with Sleep Transistors and Body Bias
Document Type
Publication order reference
YADDA identifier
bwmeta1.element.bwnjournal-article-appv123n2007kz
Identifiers
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