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Number of results
2011 | 120 | 6A | A-22-A-24

Article title

High Quality Gate Insulator/GaN Interface for Enhancement-Mode Field Effect Transistor

Content

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EN

Abstracts

EN
The capacitance-voltage measurements were applied for characterization of the semiconductor/dielectric interface of GaN MOS capacitors with SiO_2 and HfO_2/SiO_2 gate stacks. From the Terman method low density of interface traps (D_{it} ≈ 10^{11} eV^{-1} cm^{-2}) at SiO_2/GaN interface was calculated for as-deposited samples. Samples with HfO_2/SiO_2 gate stacks have higher density of interface traps as well as higher density of mobile charge and effective charge in the dielectric layers. High quality of SiO_2/GaN interface shows applicability of SiO_2 as a gate dielectric in GaN MOSFET transistors.

Keywords

Contributors

author
  • Institute of Electron Technology, al. Lotników 32/46,02-668 Warsaw, Poland
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland
author
  • Institute of Electron Technology, al. Lotników 32/46,02-668 Warsaw, Poland
  • Institute of Electron Technology, al. Lotników 32/46,02-668 Warsaw, Poland
  • Institute of Physics, Polish Academy of Sciences, al. Lotników 32/46, 02-668 Warsaw, Poland
author
  • Institute of Electron Technology, al. Lotników 32/46,02-668 Warsaw, Poland
author
  • Institute of Electron Technology, al. Lotników 32/46,02-668 Warsaw, Poland

References

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Document Type

Publication order reference

Identifiers

YADDA identifier

bwmeta1.element.bwnjournal-article-appv120n6ap05kz
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