High Quality Gate Insulator/GaN Interface for Enhancement-Mode Field Effect Transistor

• Authors: A. Taube , R. Kruszka , M. Borysiewicz , S. Gierałtowska , E. Kamińska , A. Piotrowska
• Languages of publication: EN

Abstracts

EN

The capacitance-voltage measurements were applied for characterization of the semiconductor/dielectric interface of GaN MOS capacitors with SiO_2 and HfO_2/SiO_2 gate stacks. From the Terman method low density of interface traps (D_{it} ≈ 10^{11} eV^{-1} cm^{-2}) at SiO_2/GaN interface was calculated for as-deposited samples. Samples with HfO_2/SiO_2 gate stacks have higher density of interface traps as well as higher density of mobile charge and effective charge in the dielectric layers. High quality of SiO_2/GaN interface shows applicability of SiO_2 as a gate dielectric in GaN MOSFET transistors.

Keywords

EN

77.55.dj   77.22.Ch   73.40.Qv   81.15.Gh   81.15.Cd  

• Publisher: Institute of Physics, Polish Academy of Sciences
• Journal: Acta Physica Polonica A
• Year: 2011
• Volume: 120
• Issue: 6A
• Pages: A-22-A-24

Dates

published

2011-12

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Identifiers

DOI

10.12693/APhysPolA.120.A-22