In this work studies of some electrical parameters of the MOS structure based on 3C-SiC substrate are presented. The effective contact potential difference ϕMS, the barrier height at the gate-dielectric interface E
BG and the flat-band in semiconductor voltage V
FB were measured using several electric and photoelectric techniques. Values of these parameters obtained on structures with different gate areas decrease monotonically with increasing parameter R, defined as the ratio of the gate perimeter to the gate area. Such behavior confirmed results obtained on MOS structures on silicon substrate and also supported our hypothesis that the mechanical stress in the dielectric layer under the metal gate causes non uniform distribution of some parameters over the gate area of MOS structure.